Section: New Software and Platforms

FloPoCo

Floating-Point Cores, but not only

Keyword: Synthesizable VHDL generator

Functional Description: The purpose of the open-source FloPoCo project is to explore the many ways in which the flexibility of the FPGA target can be exploited in the arithmetic realm.

• Participants: Florent de Dinechin and Luc Forget

• Partners: CNRS - ENS Lyon - UCBL Lyon 1 - UPVD

• Contact: Florent de Dinechin

• URL: http://flopoco.gforge.inria.fr/